RF power amplifiers, like most amplifiers, are substantially linear at small signal amplitudes. However, it is preferable to drive power amplifiers near saturation to deliver significant output power at a reasonable efficiency. As the operation of a power amplifier approaches saturation, it will become more nonlinear, and thus, exhibit more distortion in its output. Consequently, numerous “linearizer” circuits have been developed over the years in an attempt to remove the power amplifier's nonlinearity and thereby reduce the distortion in its output. Because the characteristics of the power amplifier may change over time and frequency, these linearizer circuits may be designed to adapt to present amplifier conditions. A generic power amplifier linearizer is shown in FIG. 1, and uses either predistortion circuitry, feedforward circuitry, or a combination of both, to correct for the power amplifier's nonlinearity. (The inclusion of this generic linearizer in this Background Section is not intended to imply that the circuit configuration shown therein, and variations thereof, are in the prior art.)
For example, a linearizer may use only a predistortion adjuster circuit p. As will be appreciated by those skilled in the art, in this linearizer the signal adjuster circuit s is merely a delay line ideally matching the total delay of the adjuster circuit p and the power amplifier. In this case, the distortion cancellation circuit, comprising the distortion adjuster circuit d, the error amplifier and the delay circuit, is not used—the output of the linearizer is the output of the signal power amplifier. The goal of the adjuster circuits is to predistort the power amplifier input signal so that the power amplifier output signal is proportional to the input signal of the linearizer. That is, the predistorter acts as a filter having a transfer characteristic which is the inverse of that of the power amplifier, except for a complex constant (i.e., a constant gain and phase). Because of their serial configuration, the resultant transfer characteristic of the predistorter and the power amplifier is, ideally, a constant gain and phase that depends on neither frequency nor signal level. Consequently, the output signal will be the input signal amplified by the constant gain and out of phase by a constant amount, that is, linear. Therefore, to implement such predistortion linearizers, the transfer characteristic of the power amplifier is computed and a predistortion filter having the inverse of that transfer characteristic is constructed. Preferably, the predistortion filter should also compensate for changes in the transfer function of the power amplifier, such as those caused by degraded power amplifier components.
Other linearizers use feedforward circuitry to correct for the nonlinearity in the power amplifier. A feedforward linearizer usually uses a combination of signal adjuster circuit s 110 and distortion adjuster circuit d 111 as configured in FIG. 1 (in this linearizer, predistortion adjuster p 109 is not used). In an alternative configuration, the signal adjuster circuit may be placed before the power amplifier, i.e., as adjuster circuit p 109, an example of which is shown in FIG. 7. This latter configuration advantageously compensates for any additional signal distortion caused by the signal adjuster circuit, since it will be superimposed upon the distortion caused by the power amplifier and be removed by a distortion cancellation circuit. Further, adjusters p 109, s 110, and d 111 may be used simultaneously to linearize the power amplifier.
As shown in FIG. 1, a feedforward linearizer comprises two main circuits: a signal cancellation circuit 101 and a distortion cancellation circuit 102. The RF signal is input to the signal power amplifier 103, which as discussed above, is assumed to be operating in a non-linear range and thus distorting the output signal. The signal cancellation circuit 101 ideally subtracts a linear estimate of the RF signal from the distorted power amplifier output signal so that only the nonlinear distortion signal (or “error signal”) (ve) remains. As will be appreciated to those skilled in the art, the signal pickoff points, the adder 104, and the subtractors 106 and 107 shown in FIG. 1 and other figures may be implemented by directional couplers, splitters or combiners, as appropriate. In the distortion cancellation circuit 102, the distortion signal is adjusted and amplified by error amplifier 108 to match the distortion signal component of the power amplifier output signal delayed by delay 112. The amplified distortion signal is then subtracted from the output of delay 112 by subtractor 107 to provide the linearizer output signal vo. The linearizer output signal is a substantially distortion-free amplified RF signal, the output that would have been obtained if the power amplifier were truly linear.
Generally, the adjuster circuits discussed above do not necessarily all have the same structure—adjuster circuits p 109, s 110 and d 111 may all be implemented with different circuitry. For example, the adjuster circuit p 109 may be a nonlinear polynomial filter, while the adjuster circuits s 110 and d 111 may be finite impulse response (FIR) filters. In addition, some methods of controlling these adjuster circuits may employ pilot (tone) signals generated by an optional pilot signal generator 113.
The relationship of the input and output signals of an adjuster circuit depends on the settings of one or more parameters of that adjuster circuit, as will be discussed in further detail below. During adaptation, the values of one or more internal signals of an adjuster circuit are used to determine appropriate settings for its parameters. As shown in FIG. 1, an “adaptation controller” 114 monitors the error and output signals ve and vo, and in some cases, the internal adjuster signals. (In FIG. 1 and other figures, a stroke on an arrow denotes a multiplicity of signals or a multiplicity of parameters, as the case may be.) On the basis of the monitored signal values, and in accordance with the adaptation algorithm, the adaptation controller sets the adjuster circuit parameters.
For example, a three-branch adaptive polynomial predistortion adjuster circuit p 109 is shown in FIG. 2. The upper branch 200 is linear, while the middle branch has a nonlinear cubic polynomial filter 201 and the lower branch has a nonlinear quintic polynomial filter 202, the implementation of which nonlinear filters is well known to those skilled in the art. Each branch also has a complex gain adjuster (“CGA”), respectively 203, 204, and 205, to adjust the amplitude and phase of the signal as it passes therethrough. By setting the parameters (GA, GB) of each of the CGAs, a polynomial relationship between the input and output of the adjuster circuit can be established to compensate for a memoryless nonlinearity in the power amplifier. The adaptation controller, via a known adaptation algorithm, uses the input signal, the output of the nonlinear cubic polynomial filter, the output of the nonlinear quintic polynomial filter, and the error signal (the power amplifier output signal minus an appropriately delayed version of input signal) to generate the parameters (GA, GB) for the three CGAs. Generally, the adaptation algorithm is selected to minimize a certain parameter related to the error signal (for example, its power over a predetermined time interval). Examples of such adaptation algorithms are described in more detail below.
Two possible CGA implementations are respectively shown in FIGS. 3A and 3B. The implementation shown in FIG. 3A uses polar control parameters GA and GB, where GA sets the amplitude of the attenuator 301, while GB sets the phase of the phase shifter 302. The implementation shown in FIG. 3B uses Cartesian control parameters, also designated GA and GB, where GA sets the real part of the complex gain, while GB sets the imaginary part of the complex gain. In this implementation, the input signal I is split into two signals by splitter 306, one of which is then phase-shifted by 90 degrees by phase shifter 303, while the other is not. After GA and GB are applied by mixers or attenuators 305 and 304 respectively, the signals are summed by combiner 307 to produce the CGA output signal O. U.S. Pat. No. 6,208,207 describes, in part, the linearization of these mixers and attenuators, so that desired values of complex gain can be predictably obtained by appropriate setting of the control voltages GA and GB.
For example, a three-branch adjuster circuit s 110 and a three-branch adjuster circuit d 111 in a feedforward linearizer are shown in FIG. 4. Feedforward linearizers having one or more branches in the adjuster circuits are described in U.S. Pat. Nos. 5,489,875 and 6,208,207, both of which are incorporated herein by reference. Each branch within the circuits 110 and 111, labeled “FIR adjuster”, includes a delay element (i.e., delays 401, 403 and 405 in the adjuster s 110, and delays 407, 409, and 411 in adjuster d 111) and a CGA (i.e., CGAs 402, 404 and 406 in the adjuster s 110, and CGAs 408, 410, and 412 in adjuster d 111). The delays in each branch may be different, and the sum of the parallel branches act as an analog FIR filter (also known as an analog transversal filter).
Appropriate settings of the parameters (GA, GB) of the CGAs allow the first FIR adjuster circuit 110 to mimic the linear portion of the power amplifier response, including the effects of amplifier delay and other filtering, and for frequency dependence of its own components. Ideally, the amplifier nonlinear distortion is revealed at the output of the subtractor following the first FIR adjuster circuit (ve). Appropriate settings of the parameters (GA, GB) of the second FIR adjuster circuit 111 allow it to compensate for delay and other filtering effects in the amplifier output path and for frequency dependence in its own components, and to subtract a replica of the nonlinear distortion from the delayed amplifier output. The adaptation controller 114 of FIG. 4, via a known adaptation algorithm, uses the internal signals of the branches of the signal and distortion adjuster circuits s 110 and d 111 and their respective error signals ve and vo, to compute GA and GB for each of the CGAs in the signal and distortion adjuster circuits 110 and 111. In this fashion, the linearization circuit compensates for an amplifier nonlinearity with memory. Examples of such adaptation controllers can be found in U.S. Pat. Nos. 5,489,875 and 6,208,207.
The linearizer circuits of the prior art, however, ignore a phenomenon that often determines the success or failure of the adaptation controller—the monitored signals, as measured by the adaptation controller, are not necessarily equal to their counterpart internal signals within the adjuster circuits, or to the actual error and output signals ve and vo, as the case may be. The reason is that the cables, circuit board traces, and other components in the signal paths that convey the internal adjuster circuit signals, or the error and output signals ve and vo, to the adaptation controller introduce inadvertent phase and amplitude changes into those signals. The true situation is represented in FIGS. 6 and 8, where these phase and amplitude changes are generically modeled as “observation filters” (601–603, 804, 805). In addition, Hp(f) 601, Hs(f) 602 and Hd(f) 603 may each be considered to comprise a bank of “observation subfilters,” such as hp1(f), hp2(f), etc., each observation subfilter modeling the transformation of a particular internal signal of an adjuster circuit into a corresponding monitor signal (for example, one observation subfilter per branch of a multibranch adjuster). The characteristics of these observation filters or subfilters are initially unknown.
In the simplest case, the observation filters or subfilters may represent fixed amplitude and phase changes on each of the signal paths. In a more complex case, however, the amplitude and phase changes, and thus the observation filters, can be frequency-dependent. For example, a three-branch signal adjuster p 109 located in front of the power amplifier 103 is shown in FIG. 7. This adjuster circuit is constructed so that each branch k (k=0, 1, 2) contains a frequency-dependent filter gk(f) (701, 703 or 705), which serves as a generalization of the delay elements of an FIR adjuster, and a CGA (702, 704 or 706). (The mention of these general branch filters gk(f) in this Background Section is not intended to imply that their use in FIR adjuster circuits is known in the prior art; rather, such use is intended to be within the scope of the present invention.) Each observation subfilter hk(f) (707, 708 or 709) of observation filter Hp(f) 601 models the transformation of the internal signal on branch k into the corresponding monitor signal used by the adaptation controller.
It should be understood that placement of filters (or filter banks) as shown in FIG. 6 is just one of many ways to model the difference (inequality) between the internal signals and the monitor signals. Nevertheless, the observation filters shown in FIG. 6 are sufficient, because other ways of modeling the difference between internal signals and their corresponding monitor signals are equivalent to the representation thereto. For example, FIG. 8 shows a linearizer circuit that includes an observation filter hem(f) 804 in the path of the error signal ve output from the first subtractor 106, and an observation filter hom(f) 805 in the path of the RF output signal vo, output from the second subtractor 107, to the adaptation controller 114. These observation filters can be transformed to the representation shown in FIG. 6 by including the effect of hem(f) 804 in the branch paths of adjuster circuits p 109 and s 110, and of hom(f) 805 into the branch path of adjuster circuit d 111 and the distortion cancellation circuit reference branch.
The severity of the problem caused by the differences between the internal adjuster signals and their corresponding monitor signals can be illustrated by a simple example. FIG. 9 illustrates the signal cancellation circuit 101 of a single-branch feedforward linearizer. Specifically, the signal adjuster circuit s 110 includes a single delay 901 followed by a CGA 902. The adaptation controller 114 uses a known “stochastic gradient” algorithm (see, for example, the gradient adaptation controller disclosed in U.S. Pat. No. 5,489,875) to correlate using bandpass correlator 903 the error signal at the output of the subtractor with the monitored replica of the internal signal of the adjuster circuit, both of which are bandpass signals. The controller integrates the result using integrator 905, via loop gain amplifier 904, to provide CGA parameters GA and GB. The internal structure of a known bandpass correlator is depicted in FIG. 10, and includes a phase shifter 1001, mixers 1002 and 1003, and bandpass filters (or integrators) 1004 and 1005 (for a description of the operation of such a bandpass correlator, see FIG. 3 of U.S. Pat. No. 5,489,875 and the text corresponding thereto). In the idealized situation considered in the prior art, the monitor signal and the internal signal are equal, with Hs(f)=h=1 (906) at all frequencies, and the correlation result is a stochastic estimate of the gradient of the error signal power with respect to the CGA parameters. That is, the correlation result is proportional to the change in CGA parameter settings that would result in the greatest increase in error signal power. Sign reversal and integration causes the CGA parameters to be corrected in the direction that most decreases the error signal power, and the adaptation loop converges correctly to the setting of GA and GB that minimizes error signal power, with a time constant determined by the value K of the loop gain amplifier 904.
To continue this example, when the linearizer is implemented, it will differ from the ideal case in that the monitor signal (bandpass signal 1 of FIG. 10) will likely have unknown phase and amplitude shifts with respect to the internal adjuster signal. These shifts are represented by the complex variable h (906) in FIG. 9. If h has a phase shift of 180 degrees, then the correlation result will be negated, and the correction to the CGA parameters will be made in a direction that maximally increases, rather than decreases, the error signal power. This, in turn, will cause the circuit to diverge from its ideal setting. More generally, a phase shift in h of over 90 degrees will cause the circuit to diverge. A phase shift value of greater than zero degrees, but less than 90 degrees, will allow the circuit to converge to its ideal setting, but with decreasing rapidity as it approaches 90 degrees.
The same problem may afflict adaptation controllers based on other algorithms that exploit the relationships among monitored signals in order to make corrections to CGA settings. For example, a least squares (“LS”) algorithm or a recursive LS algorithm may also diverge (or converge more slowly) under the same phase shift conditions asset forth above for the stochastic gradient algorithm.
In a multibranch adjuster circuit, for example, the polynomial predistorter circuit of FIG. 2 or the feedforward circuit of FIGS. 4 and 6, there are further consequences of the lack of equality between an internal adjuster signal and its corresponding monitor signal. Signals carried on the branches of an adjuster tend to be highly correlated, making stochastic gradient adaptation slow. The remedy is linear transformation of the multiple branch signals to produce a multiplicity of decorrelated signals. The decorrelated signals, or modes, are then adapted individually to provide a much faster convergence. However, the lack of equality between internal and corresponding monitor signals, as modeled by the filter banks in FIG. 6, reduces the ability to decorrelate those signals completely. This results in branch signals with residual correlation, thus reducing the benefits of decorrelation. Furthermore, if the internal and monitor signals are not equal, unfavorable phase and amplitude relationships among the filters may cause one or more of the decorrelation mode adaptations to diverge, preventing adaptation altogether.
In addition, in a stochastic gradient controller, if wide power disparities exist among the decorrelated signals, stronger signals may interfere or “mask” the weaker signals, degrading the latter and slowing adaptation. To reduce this masking problem, a “partial gradient” algorithm may be used by the adaptation controller (see, for example, the partial gradient adaptation controller disclosed in U.S. Pat. No. 5,489,875), in which the correlation between two bandpass signals is approximated as a sum of partial correlations taken over limited bandwidths at selected frequencies. By making the frequencies selectable, correlations may be calculated at frequencies that do not contain strong signals, so that the strong signals do not mask the weak signals. In addition, a digital signal processor (DSP) may be used to perform correlation, because the correlations are taken over limited bandwidths. This eliminates the DC offset that otherwise appears in the output of a correlator implemented by directly mixing two bandpass signals.
FIG. 11 illustrates a partial correlator, in which local oscillators 1101 and 1102 select the frequency of the partial correlation. Frequency shifting and bandpass filtering are performed by the mixer/bandpass filter combinations 1103/1107, 1104/1108, 1105/1109, and 1106/1110. The signals output by the bandpass filters 1109 and 1110 are digitally converted, respectively, by A/D converters 1111 and 1112. Those digital signals are bandpass correlated by DSP 1113 to produce the real and imaginary components of the partial correlation. (See, for example, FIG. 9 of U.S. Pat. No. 5,489,875 for a description of the operation of a partial correlator similar to that shown in FIG. 11 herein.) However, as in the case of the stochastic gradient adaptation controller, a lack of equality between the internal signals and their corresponding monitor signals (for example, bandpass signal 1) may cause either divergence or slowed convergence of the partial gradient adaptation controller of FIG. 11.
Accordingly, self-calibrated power amplifier linearizers are desired to compensate for the lack of equality between the internal adjuster signals and their corresponding monitor signals, and to overcome the resulting divergence, or slowed convergence, of the adaptation controllers used therein.